Logic design validation via simulation and automatic test pattern generation

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 16, Issue 6, 2000, Pages 575-589

  Al Asaad, Hussain ^a,c   Hayes, John P ^b,c,d,e,f,g  

^a Davis   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

^c Department of Ecology and Evolutionary Biology   (United States)

^d NATIONAL UNIVERSITY OF IRELAND   (Ireland)

^e UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^f SHELL GLOBAL SOLUTIONS INTERNATIONAL B V   (United States)

^g UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; DESIGN FOR TESTABILITY; ERROR ANALYSIS; FAILURE ANALYSIS; SEQUENTIAL CIRCUITS;

AUTOMATIC TEST PATTERN GENERATION; GATE COUNT ERROR; GATE SUBSTITUTION ERROR; INPUT COUNT ERROR; LATCH COUNT ERROR; SINGLE STUCK LINE; WRONG INPUT ERROR;

LOGIC DESIGN;

EID: 0034510791     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008302118244     Document Type: Article

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