Modeling the driver load in the presence of process variations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 10, 2006, Pages 2264-2275

  Wang, Janet M ^a   Li, Jun ^b   Yanamanamanda, Satish ^c,d   Vakati, Lakshmi K ^c,d   Muchherla, Kishore K ^c,d  

^a University of Arizona   (United States)

^b Anova Solutions Inc   (United States)

^c UNIVERSITY OF ARIZONA   (United States)

^d MICRON TECHNOLOGY INC   (United States)

Author keywords

Driver equivalent resistance; Inductance effect evaluation criteria; Interconnect driving point admittance; Multiple effective capacitance; Probability collocation method (PCM); Process variation

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; CONTROL NONLINEARITIES; ELECTRIC RESISTANCE; INDUCTANCE; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; MONTE CARLO METHODS; NATURAL FREQUENCIES; POLYNOMIALS; PROBABILISTIC LOGICS; WAVEFORM ANALYSIS;

DRIVER EQUIVALENT RESISTANCE; INDUCTANCE EFFECT EVALUATION CRITERIA; INTERCONNECT DRIVING-POINT ADMITTANCE; MULTIPLE EFFECTIVE CAPACITANCE; PROBABILITY COLLOCATION METHOD (PCM); PROCESS VARIATION;

ELECTRIC LOADS;

EID: 33748323310     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.862739     Document Type: Article

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