Modeling the impact of back-end process variation on circuit performance

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 1999, Pages 58-61

  Sylvester, Dennis ^a   Nakagawa, O Sam ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CROSSTALK; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; MONTE CARLO METHODS; PERFORMANCE; RANDOM PROCESSES; SPURIOUS SIGNAL NOISE; TIMING CIRCUITS;

CLOCK DISTRIBUTION NETWORK; INTERCONNECT PROCESS VARIATION;

INTEGRATED CIRCUIT TESTING;

EID: 0032599268     PISSN: 1524766X     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (15)