Statistical gate delay model considering Multiple Input Switching

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 658-663

  Agarwal, Aseem ^a   Dartu, Florentin ^b   Blaauw, David ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Algorithms; Performance; Reliability

Indexed keywords

ALGORITHMS; BENCHMARKING; COMPUTER SIMULATION; ERROR CORRECTION; GATES (TRANSISTOR); MATHEMATICAL MODELS; MICROELECTROMECHANICAL DEVICES; OPTIMIZATION; RELIABILITY; STATISTICAL METHODS;

MULTIPLE INPUT SWITCHING (MIS); STATISTICAL GATE DELAY MODEL; STATISTICAL STATIC TIMING ANALYSIS (SSTA);

SWITCHING CIRCUITS;

EID: 4444374515     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996746     Document Type: Conference Paper

References (12)

1. A. Devgan, C. Kashyap, "Block-based Static Timing Analysis with Uncertainty," ICCAD 2003, pp.607-614
2. Hongliang Chang, S. Sapatnekar, "Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-like Traversal," ICCAD 2003, pp.621-625
3. A. Agarwal, D. Blaauw, V. Zolotov, "Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations," ICCAD 2003, pp.900-907
4. A. Agarwal, D. Blaauw, V. Zolotov, S. Vrudhula, "Computation and Refinement of Statistical Bounds on Circuit Delay," DAC 2003, pp. 348-353.
5. L. Sheffer, "Explicit Computation of Performance as a Function of Process Variation", Int. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, TAU 2002.
6. M. Berkelaar, "Statistical Delay Calculation, a Linear Time Method," Proceedings of TAU 97, Austin, TX, December 1997
7. J.J Liou, K.T. Cheng, S. Kundu, A. Krstic, "Fast Statistical Timing Analysis By Probabilistic Event Propagation", DAC 2001
8. M. Orshansky, K. Keutzer, "A general probabilistic framework for worst-case timing analysis", Proc. DAC 2002.
9. A. Gattiker, S.Nassif, R.Dinakar, C.Long "Timing Yield Estimation from Static Timing Analysis," Proc., ISQED 2001
10. J.A.G Jess, K. Kalafala, S.R. Naidu, R.H.J.M Otten, C. Visweswariah, "Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits," Proceedings ACM/IEEE Design Automation Conference, 2003.
11. V. Chandramouli, Karem A. Sakallah "Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation delay and Transition Time", Design Automation Conf., 1996
12. Y.-H. Jun, K. Jun, S.-B. Park, "An Accurate and Efficient Delay time Modeling for MOS Logic Circuits using Polynomial Approximation", IEEE Trans. on CAD., 9(6), 1989, pp. 1027-1032.