0.13-μm RF CMOS and varactors performance optimization by multiple gate layouts

IEEE Transactions on Electron Devices

Volumn 51, Issue 12, 2004, Pages 2181-2185

  Ho, Chien Chih ^b   Kuo, Chin Wei ^b   Chan, Yi Jen ^a   Lien, Wan Yih ^b   Guo, J C ^c  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^c NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

0.13. m CMOS; N Fmin; RF power; Varactor

Indexed keywords

CAPACITANCE; ELECTRIC RESISTANCE; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; VARACTORS;

MULTIPLE GATE LAYOUT; OPTIMIZED GATE LAYOUT;

CMOS INTEGRATED CIRCUITS;

EID: 10644227835     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.839868     Document Type: Article

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