Characteristics and physical mechanisms of positive bias and temperature stress-induced drain current degradation in HfSiON nMOSFETs

IEEE Transactions on Electron Devices

Volumn 53, Issue 6, 2006, Pages 1340-1346

  Chan, Chien Tai ^a   Tang, Chun Jung ^a   Wang, Tahui ^a   Wang, Howard C H ^b   Tang, Denny D ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

HfSiON; Positive bias temperature instability (PBTI); Transient measurement; Trap generation; Two stage degradation

Indexed keywords

DEGRADATION; DIELECTRIC MATERIALS; GATES (TRANSISTOR); HAFNIUM COMPOUNDS; PERMITTIVITY; STRAIN; STRESS ANALYSIS;

POSITIVE TEMPERATURE INSTABILITY; TRANSIENT MEASUREMENT; TRAP GENERATION; TWO-STAGE DEGRADATION;

MOSFET DEVICES;

EID: 33744819496     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.874160     Document Type: Article

References (18)

1. H. Iwai, S. Ohmi, S. Akama, C. Ohshima, A. Kikuchi, I. Kashiwagi, J. Taguchi, H. Yamamoto, J. Tonotani, Y. Kim, I. Ueda, A. Kuriyama, and Y. Yoshihara, "Advanced gate dielectric materials for sub-100 nm CMOS," in IEDM Tech. Dig., 2002, pp. 625-628.
2. H. C.-H. Wang, S.-J. Chen, M.-F. Wang, P.-Y. Tsai, C.-W. Tsai, T.-W. Wang, S. M. Ting, T.-H. Hou, P.-S. Lim, H.-J. Lin, Y. Jin, H.-J. Tao, S.-C. Chen, C. H. Diaz, M.-S. Liang, and C. Hu, "Low power device technology with SiGe channel, HfSiON, and poly-Si gate," in IEDM Tech. Dig., 2004, pp. 161-164.
3. 2 stack," in Proc. Int. Reliab. Phys. Symp., 2004, pp. 181-187.
4. 2 stacks," in VLSI Symp. Tech. Dig., 2004, pp. 140-141.
5. 2 reliability and yield," in IEDM Tech. Dig., 2003, pp. 935-938.
6. 2 stacked gate dielectrics dominated by the generated subordinate carrier injection," in IEDM Tech. Dig., 2004, pp. 721-724.
7. 2 stacked gate dielectrics," in VLSI Symp. Tech. Dig., 2005, pp. 166-167.
8. T. Yamaguchi, I. Hirano, R. Iijima, K. Sekine, M. Takayanagi, K. Eguchi, Y. Mitani, and N. Fukushima, "Thermochemical understanding of dielectric breakdown in HfSiON with current acceleration," in Proc. Int. Reliab. Phys. Symp., 2005, pp. 67-74.
9. S. Zafar, A. Callegari, E. Gusev, and M. V. Fischetti, "Charge trapping in high K gate dielectric stacks," in IEDM Tech. Dig., 2002, pp. 517-520.
10. S. Zafar, A. Callegari, E. Gusev, and M. V. Fischetti, "Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks," J. Appl. Phys., vol. 93, no. 11, pp. 9298-9303, Jun. 2003.
11. A. Shanware, M. R. Visokay, J. J. Chambers, A. L. P. Rotondaro, H. Bu, M. J. Bevan, R. Khamankar, S. Aur, P. E. Nicollian, J. McPherson, and L. Colombo, "Evaluation of the positive bias temperature stress stability in HfSiON gate dielectrics," in Proc. Int. Reliab. Phys. Symp., 2003, pp. 208-213.
12. C. T. Chan, C. J. Tang, C. H. Kuo, H. C. Ma, C. W. Tsai, H. C. H. Wang, M. H. Chi, and T. Wang, "Single-electron emission of traps in HfSiON as high-k gate dielectric for MOSFETs," in Proc. Int. Reliab. Phys. Symp., 2005, pp. 41-44.
13. C. T. Chan, C. J. Tang, T. Wang, H. C.-H. Wang, and D. D. Tang, "Positive bias and temperature stress induced two-stage drain current degradation in HfSiON nMOSFET's," in IEDM Tech. Dig., 2005, pp. 571-574.
14. N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai, and T. Horiuchi, "The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling," in VLSI Symp. Tech. Dig., 1999, pp. 73-74.
15. H. C.-H. Wang, C. W. Tsai, S. J. Chen, C. T. Chan, H. J. Lin, Y. Jin, H. J. Tao, S. C. Chen, C. H. Diaz, T. Ong, A. S. Oates, M. S. Liang, and M. H. Chi, "Reliability of HfSiON as gate dielectric for advanced CMOS technology," in VLSI Symp. Tech. Dig., 2005, pp. 170-171.
16. C. T. Chan, H. C. Ma, C. J. Tang, and T. Wang, "Investigation of post-NBTI stress recovery in pMOSFETs by direct measurement of single oxide charge de-trapping," in VLSI Symp. Tech. Dig., 2005, pp. 90-91.
17. T. Wang, C. T. Chan, C. J. Tang, C. W. Tsai, H. C.-H. Wang, M. H. Chi, and D. D. Tang, "A novel transient characterization technique to investigate trap properties in HfSiON gate dielectric MOSFETs - From single electron emission to PBTI recovery transient," IEEE Trans. Electron Devices, to be published, 2006.
18. T. Yang, M. F. Li, C. Shen, C. H. Ang, C. Zhu, Y. C. Yeo, G. Samudra, S. C. Rustagi, M. B. Yu, and D. L. Kwong, "Fast and slow dynamic NBTI components in p-MOSFET with SiON dielectric and their impact on device life-time and circuit application," in VLSI Symp. Tech. Dig., 2005, pp. 92-93.