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Volumn 2005, Issue , 2005, Pages 22-27

An unified fault model and test generation procedure for interconnect opens and bridges

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTER SIMULATION; INTEGRATED CIRCUITS; INTERCONNECTION NETWORKS;

EID: 33744496055     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETS.2005.6     Document Type: Conference Paper
Times cited : (38)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.