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Volumn , Issue , 2004, Pages 669-678

Evaluation of the quality of N-detect scan ATPG patterns on a processor

Author keywords

[No Author keywords available]

Indexed keywords

FAULT DETECTION; PRODUCT QUALITY; SIGNAL STATES; TEST PATTERNS; TEST QUALITY;

EID: 18144425772     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (45)

References (15)
  • 1
    • 0034482031 scopus 로고    scopus 로고
    • Stuck-feult tests vs. actual defects
    • E. J. McCluskey and Chao-Wen Tseng, "Stuck-feult tests vs. actual defects", Proc. ITC, 2000, pp.336-342.
    • (2000) Proc. ITC , pp. 336-342
    • McCluskey, E.J.1    Tseng, C.-W.2
  • 2
    • 0030686636 scopus 로고    scopus 로고
    • An experimental study comparing the relative effectiveness of functional, scan, IDDq, and delay fault testing
    • P. Nigh, W. Needham, K. Butler, P. Maxwell, R. Aitken, "An Experimental Study Comparing the Relative Effectiveness of Functional, Scan, IDDq, and Delay Fault Testing", Proc. VTS, 1997, pp. 459-464.
    • (1997) Proc. VTS , pp. 459-464
    • Nigh, P.1    Needham, W.2    Butler, K.3    Maxwell, P.4    Aitken, R.5
  • 3
    • 0024124693 scopus 로고
    • Extraction and simulation of realistic faults using inductive fault analysis
    • Oct
    • J. F. Ferguson and J. P. Shen, "Extraction and Simulation of Realistic Faults using Inductive Fault Analysis", IEEE International Test Conference, Oct 1988, pp. 475-484.
    • (1988) IEEE International Test Conference , pp. 475-484
    • Ferguson, J.F.1    Shen, J.P.2
  • 4
    • 0002936338 scopus 로고
    • CARAFE: An inductive fault analysis tool for CMOS VLSI circuits
    • Apr.
    • A. L. Jee and J. F. Ferguson, "CARAFE: An Inductive Fault Analysis Tool for CMOS VLSI Circuits", IEEE VLSI Test Symposium, Apr. 1992, pp. 92-98.
    • (1992) IEEE VLSI Test Symposium , pp. 92-98
    • Jee, A.L.1    Ferguson, J.F.2
  • 5
    • 0034482034 scopus 로고    scopus 로고
    • A scalable and efficient methodology to extract two node bridges from large industrial circuits
    • Oct
    • S. T. Zachariah and S. Chakravarty, "A Scalable and Efficient Methodology to Extract Two Node Bridges from Large Industrial Circuits", IEEE International Test Conference, Oct 2000, pp. 750-759.
    • (2000) IEEE International Test Conference , pp. 750-759
    • Zachariah, S.T.1    Chakravarty, S.2
  • 8
    • 0029510949 scopus 로고
    • An experimental test chip to evaluate test techniques experimental results
    • Oct
    • S. C. Ma, P. Franco and E. J. McCluskey, "An Experimental Test Chip to Evaluate Test Techniques Experimental Results," Proc. ITC, Oct 1995, pp.663-672.
    • (1995) Proc. ITC , pp. 663-672
    • Ma, S.C.1    Franco, P.2    McCluskey, E.J.3
  • 11
    • 0032313243 scopus 로고    scopus 로고
    • Stuck-at Tuple-detection: A fault model based on stuck-at faults for improved detect coverage
    • I. Pomeranz, S.M.Reddy, "Stuck-at Tuple-detection: a fault model based on stuck-at faults for improved detect coverage", Proc. VTS 1998, pp. 289-294.
    • Proc. VTS 1998 , pp. 289-294
    • Pomeranz, I.1    Reddy, S.M.2
  • 12
    • 0030685579 scopus 로고    scopus 로고
    • On n-detectoin test sequences for synchronous sequential circuits
    • I. Pomeranz, S. M. Reddy, "On n-detectoin test sequences for synchronous sequential circuits", Proc. VTS, 1997, pp. 336-342.
    • (1997) Proc. VTS , pp. 336-342
    • Pomeranz, I.1    Reddy, S.M.2
  • 14
    • 0142184765 scopus 로고    scopus 로고
    • Analyzing the effectiveness of multiple-detect test set
    • R. D. Blanton, K N. Dwaarakanth and A. B. Shah "Analyzing the Effectiveness of Multiple-Detect Test Set", Proc. ITC, 2003, pp. 876-885.
    • (2003) Proc. ITC , pp. 876-885
    • Blanton, R.D.1    Dwaarakanth, K.N.2    Shah, A.B.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.