On testing of interconnect open defects in combinational logic circuits with stems of large fanout

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 83-89

  Reddy, Sudhakar M ^a   Pomeranz, Irith ^b   Tang, Huaxing ^a   Kajihara, Seiji ^c   Kinoshita, Kozo ^d  

^a UNIVERSITY OF IOWA   (United States)

^b PURDUE UNIVERSITY   (United States)

^c KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^d OSAKA GAKUIN UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; LOGIC GATES; MATHEMATICAL MODELS; SEQUENTIAL CIRCUITS;

GATE LEVEL FAULT MODEL; INTERCONNECT OPEN DEFECTS; TEST GENERATION;

COMBINATORIAL CIRCUITS;

EID: 0036446204     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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