Fault models for speed failures caused by bridges and opens

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 373-378

  Chakravarty, S ^a   Jain, A ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Bridge circuits; Circuit faults; Circuit testing; Combinational circuits; Delay; Frequency; Integrated circuit interconnections; Microprocessors; Semiconductor device modeling; Sequential circuits

Indexed keywords

BRIDGE CIRCUITS; CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; DELAY CIRCUITS; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE TESTING; SEMICONDUCTOR DEVICES; SEQUENTIAL CIRCUITS; SPEED;

CIRCUIT FAULTS; CIRCUIT TESTING; DELAY; FREQUENCY; INTEGRATED CIRCUIT INTERCONNECTIONS;

VLSI CIRCUITS;

EID: 84948428485     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011167     Document Type: Conference Paper

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