A testable BIST design for PLL

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn 2003-January, Issue , 2003, Pages 204-207

  Chang, Yeong Jar ^a   Lin, Shen Tien ^a   Luo, Kun Lun ^a   Wu, Wen Ching ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; DESIGN; ECONOMIC AND SOCIAL EFFECTS; INTEGRATED CIRCUIT TESTING; JITTER; TIMING JITTER;

ANALOG CLOCKS; DESIGN FOR TEST; FAULT COVERAGES; HIGH-ACCURACY; HIGH-PRECISION; PHASE LOCK LOOP (PLL); TEST INTEGRATION; TEST PATTERN;

BUILT-IN SELF TEST;

EID: 84944672509     PISSN: 19308868     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2003.1252588     Document Type: Conference Paper

References (8)

1. Stephen Sumer & Aubin Roy, LogicVision, Inc, "BIST for phase-locked loops in digital applications", ITC, 1999.
2. Jun-Jia Chen, Kuen-Jong Lee, "PLL with On-Chip Jitter Measurement", Master Thesis, NCKU/EE Taiwan, June, 2001.
3. Fluence inc. homepage, www.fluence.com
4. S. Tabatabaei and A. Ivanov, "Embedded Timing Analysis: A SOC Infrastructure", IEEE Design and Test of Computers, May-June. 2002.
5. Antonio H. Chan and Gordon W. Roberts, "A Synthesizable, Fast and High-resolution Timing Measurement Device Using a Component-invariant Vernier Delay Line", ITC, 2001
6. John A. McNeill, "Jitter in Ring Oscillators", IEEE JSSC, June, 1997.
7. Nelson Soo, "Jitter Measurement Techniques", Application Brief, Pericom inc., 2000.
8. Terng-Yin Hsu, Terng-Ren Hsu, Chung-Cheng Wang, Yi-Chuan Liu, Chen-Yi Lee, "Design of a wide-band frequency synthesizer based on TDC. and DVC techniques", IEEE JSSC, Oct. 2002.