Optimal bus sizing in migration of processor design

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 5, 2006, Pages 1089-1100

  Wimer, Shmuel ^a   Michaely, Shay ^b   Moiseev, Konstantin ^b   Kolodny, Avinoam ^b  

^a INTEL CORPORATION   (Israel)

^b TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

Integrated circuit layout; Interconnections; Timing

Indexed keywords

ALGORITHMS; INTERCONNECTION NETWORKS; ITERATIVE METHODS; MICROPROCESSOR CHIPS; OPTIMIZATION; TIMING CIRCUITS;

ITERATIVE ALGORITHM; OPTIMALLY-TUNED BUS LAYOUT; SIGNAL BUSES;

INTEGRATED CIRCUIT LAYOUT;

EID: 33646508494     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2006.869902     Document Type: Article

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