Physics-based modelling and simulation of dual material gate stack (DUMGAS) MOSFET

Electronics Letters

Volumn 39, Issue 1, 2003, Pages 155-157

  Saxena, M ^a   Haldar, S ^b   Gupta, M ^c   Gupta, R S ^c  

^a UNIVERSITY OF DELHI   (India)

^b UNIVERSITY OF DELHI   (India)

^c UNIVERSITY OF DELHI   (India)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC FIELDS; ELECTRON TRANSPORT PROPERTIES; INTERFACES (MATERIALS); LEAKAGE CURRENTS; MATHEMATICAL MODELS;

SHORT-CHANNEL EFFECTS;

MOSFET DEVICES;

EID: 0037427063     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20030007     Document Type: Article

References (5)

1. LONG, W., OU, H., KUO, J.M., and CHEN, K.K.: 'Dual material gate (DMG) field effect transistor', IEEE Trans. Electron Devices, 1999, 46, (5), pp. 865-870
2. CHENG, B., CAO, M., RAO, R., INANI, A., VOORDE, P.V, GREENE, W.M., STORK, J.M.C., YU, Z., ZEITZOFF, P.M., and WOO, J.C.S.: 'The impact of high-k gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs', IEEE Trans. Electron. Devices, 1999, 46, (7), pp. 1537-1544
3. GUSEV, E.P., BUCHANAN, D.A., CARTIER, E., KUMAR, A., DIMARIA, D., GUHA, S., CALLEGARI, A., ZAFAR, S., JAMISON, P.C., NEUMAYER, D.A., COPEL, M., GRIBELYUK, M.A., SCHMIDT, H.O., D'EMIC, C., KOZLOWSKI, P., CHAN, K., BOJARCZUK, N., RAGNARSSON, L-A.̊, RONSHEIM, P., RIM, K., FLEMING, R.J., MOCUTA, A., and AJMERA, A.: 'Ultrathin high-K gate stacks for advanced CMOS devices'. IEDM Tech. Dig., 2001
4. SILVACO International, ATLAS: 2D Device Simulator
5. SUZUKI, K.: 'Short channel MOSFET using a universal channel depletion width parameter', IEEE Trans. Electron. Devices, 2000, 47, (6), pp. 1202-1208