Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 3, 2005, Pages 363-381

  Mukhopadhyay, Saibal ^a   Raychowdhury, Arijit ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Band to band tunneling (BTBT); Doping profile; Estimation; Gate direct tunneling; Halo doping; Subthreshold leakage; Technology scaling

Indexed keywords

ELECTRONS; ESTIMATION; GATES (TRANSISTOR); LEAKAGE CURRENTS; LOGIC CIRCUITS; MATHEMATICAL MODELS; MOSFET DEVICES; NANOSTRUCTURED MATERIALS; QUANTUM THEORY; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; THRESHOLD VOLTAGE; TRANSISTORS;

BAND-TO-BAND TUNNELING (BTBT); DOPING PROFILES; GATE DIRECT TUNNELING; HALO DOPING; SUBTHRESHOLD LEAKAGE; TECHNOLOGY SCALING;

CMOS INTEGRATED CIRCUITS;

EID: 15244338765     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.842810     Document Type: Article

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