Line coverage of path delay faults

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 5, 2000, Pages 610-614

  Majhi, Ananta K ^a,b   Agrawal, Vishwani D ^c   Jacob, James ^a,d   Patnaik, Lalit M ^a  

^a INDIAN INSTITUTE OF SCIENCE   (India)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

^c LUCENT TECHNOLOGIES   (United States)

^d INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; C (PROGRAMMING LANGUAGE); COMPUTER SIMULATION; DELAY CIRCUITS; GATES (TRANSISTOR); RELIABILITY; VLSI CIRCUITS;

AUTOMATIC TEST PATTERN GENERATION; FAULT COVERAGE; FAULT MODELING; PATH DELAY FAULTS; VLSI TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 0034289950     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.894166     Document Type: Article

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