Selection of potentially testable path delay faults for test generation

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 376-384

  Murakami, Atsushi ^a   Kajihara, Seiji ^a   Sasao, Tsutomu ^a   Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; ITERATIVE METHODS; LOGIC CIRCUITS; VLSI CIRCUITS;

PATH DELAY FAULTS; PATH SELECTION; PRIMITIVE FAULTS; TEST GENERATION;

INTEGRATED CIRCUIT TESTING;

EID: 0034479555     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)