Finding a small set of longest testable paths that cover every gate

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 974-982

  Sharma, Manish ^a   Patel, Janak H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; ELECTRIC NETWORK TOPOLOGY; GRAPH THEORY; HEURISTIC METHODS; LOGIC GATES; SEQUENTIAL CIRCUITS;

AUTOMATIC TEST PATTERN GENERATION; DELAY FAULT TEST; DIRECTED ACYCLIC GRAPH; GRAPH TRAVERSAL ALGORITHM; SEARCH SPACE PRUNING TECHNIQUE;

INTEGRATED CIRCUIT TESTING;

EID: 0036443068     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

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