Understanding video pixel processing applications for flexible implementations

Proceedings - Euromicro Symposium on Digital System Design, DSD 2003

Volumn , Issue , 2003, Pages 392-401

  Gangwal, Om Prakash ^a   Janssen, J ^b   Rathnam, S ^b   Bellers, E ^b   Duranton, M ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

AUDIO ACOUSTICS; ENCODING (SYMBOLS); FIR FILTERS; IMPULSE RESPONSE; MEDIAN FILTERS; MOTION PICTURE EXPERTS GROUP STANDARDS; NOISE ABATEMENT; PARALLEL PROCESSING SYSTEMS; PIXELS; SIGNAL ENCODING; SYSTEM-ON-CHIP; SYSTEMS ANALYSIS; TABLE LOOKUP;

COMPUTATIONAL GRANULARITY; COMPUTATIONAL REQUIREMENTS; DATA-LEVEL PARALLELISM; EFFICIENT IMPLEMENTATION; INNOVATIVE ALGORITHMS; MEDIA PROCESSING SYSTEMS; PROGRAMMABLE MEDIA PROCESSORS; PROGRAMMABLE PROCESSORS;

VIDEO SIGNAL PROCESSING;

ALGORITHMS; COMPUTATION; DATA PROCESSING; DECISION MAKING; IMAGE ANALYSIS;

EID: 84944319385     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2003.1231972     Document Type: Conference Paper

References (27)

1. S. Dutta, R. Jensen, A. Rieckmann, Viper: A Multiprocessor SoC for Advanced Set-Top Box and Digital TV Systems, IEEE Design and Test of Computers, Vol. 18, Sep./Oct. 2001, pp 21-31.
2. E. G. T. Jaspers, P. H. N. de With, J.G.W.M. Janssen, A Flexible Heterogeneous Video Processor System for Television Applications, IEEE Transactions on Consumer Electronics, Vol. 45, Feb. 1999, pp. 1-12.
3. M. Brett et. al, Video Processing for Single Chip DVB Decode, IEEE Transactions on Consumer Electronics, Vol. 47, Aug. 2001, pp. 385-393.
4. M. Schu, et. al, System On Silicon-IC for Motion Compensated Scan Rate Conversion, Picture-In-Picture Processing, Split Screen Applications And Display Processing, IEEE Transactions on Consumer Electronics, Vol. 45, Aug.1999, pp. 842-850.
5. M. Schu, et. al, System-on-Silicon Solution for High Quality Consumer Video Processing- The Next Generation, IEEE Transactions on Consumer Electronics, Vol. 47, Aug. 2001, pp. 412-419.
6. G. de Haan and J. Kettenis, System-on-Silicon for High Quality Display Format Conversion and Video Enhancement', Proc of ISCE'02, Sep. 2002, pp. E1-E6.
7. R. Kramer, Consumer Electronics as Silicon Engine, International Electron Devices Meeting (IEDM) 1999, pp. 3-7.
8. E. B. Bellers, De-Interlacing- A Contribution to the Interlaced Versus Progressive Video Debate, PhD Thesis, Philips Research, the Netherlands, 1999
9. H. Yamauchi, et. al, Single Chip Video Processor for Digital HDTV, IEEE Transactions on Consumer Electronics, Vol. 47, Aug. 2001, pp. 394-404.
10. M. Rudack, et. al, A Large-Area Integrated Multiprocessor System for Video Applications, IEEE Design and Test of Computers, Jan./Feb. 2002, pp 6-17.
11. R. Bhargava et. al, Characterization of MMX-enhanced DSP and Multimedia Applications on a General Purpose Processor, Digest of Workshop on Performance Analysis and Its Impact on Design (PAID98), Barcelona, Spain, July 1998
12. J. Fritts and W. Wolf and B. Liu, Understanding Multimedia Application Characteristics for Designing Programmable Media Processors, SPIE Photonics West, Media Processors '99, San Jose, CA, January 1999, pp. 2-13.
13. R. Bhargava et al. Evaluating MMX Technology using DSP and Multimedia Applications, In MICRO-31, Dec 1998, pp. 37-46.
14. P. Ranganathan, et. al, Performance of Image and Video Processing with General-Purpose and Media ISA Extensions. International Symposium on Computer Architecture, May 1999, pp. 124-135.
15. H. Nguyen and L. K. John, Exploiting SIMD Parallelism in DSP and Multimedia Algorithm Using the AltiVec Technology, International Conference on Supercomputing, 1999, pp. 11-20.
16. G. de Haan and R. Lodder, De-interlacing of Video Data using Motion Vectors and Edge Information, Digest of the ICCE'02, Jun. 2002, pp. 70-71.
17. G. De Haan, IC for Motion-Compensated De-interlacing, Noise Reduction, and Picture-Rate Upconversion, IEEE Transactions on Consumer Electronics, Vol. 45, Aug. 1999, pp. 617-624.
18. G. De Haan, and E. B. Bellers, De-interlacing - an Overview, Proceeding of the IEEE, Vol. 86, No. 9, Sep. 1998, pp. 1839-1857.
19. A.K. Riemens, R.J. Schutten, K.A. Vissers, High Speed Video Deinterlacing with a Programmable Trimedia VLIW Core, Proc. Of the ICSPAT'97, Sep. 1997, San Diego, pp. 1375-1380.
20. International Technology Roadmap for Semiconductors (ITRS) roadmap, http://public.itrs.net/.
21. O.A. Ojo and T.G. Kwaalitall-Spassova, An Algorithm for Integrated Noise Reduction and Sharpness Enhancement, IEEE Transactions on Consumer Electronics, Vol. 46, Aug.2000, pp. 474-480.
22. G. De Haan, T.G. Kwaalitall-Spassova, M.M. Larragy et al., Television Noise Reduction IC, IEEE Transactions on Consumer Electronics, Vol. 44, Feb. 1998, pp. 143-153.
23. G. de Haan, Video Processing for Multimedia Systems, ISBN: 90-9014015-8, Eindhoven Sep. 2000.
24. G. de Haan, P.W.A.C Biezen, H. Huijgen, and O.A. Ojo, "True Motion Estimation with 3-D Recursive Search Block-Matching", IEEE Tr. on Circuits and Systems for Video Technology, Vol. 3, October 1993, pp. 368-388.
25. C. Hentschel and D. La Hei, Effective Peaking Filter and Its Implementation on a Programmable Architecture, IEEE Transactions on Consumer Electronics, Vol. 47, Feb. 2001, pp. 33-39.
26. Philips Semiconductors, Data sheet SAA4978H; Picture Improved Combined Network (PICNIC), 1999.
27. A. A. Abbo & R. P. Kleihorst, Smart Cameras: Architectural Challenges, Proceedings of ACIVS 2002 (Advanced Concepts for Intelligent Vision Systems), Ghent, Belgium, September 9-11, 2002.