Integrating DFT in the physical synthesis flow

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 788-795

  Guiller, L ^a   Neuveux, F ^a   Duggirala, S ^a   Chandramouli, R ^a   Kapur, R ^a  

^a SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; FLIP FLOP CIRCUITS; GRAPH THEORY; HEURISTIC METHODS; LOGIC DESIGN; RANDOM ACCESS STORAGE; TRAVELING SALESMAN PROBLEM;

PHYSICAL SYNTHESIS FLOW; SCAN CHAIN PARTITIONING; TIMING-DRIVEN SCAN ORDERING;

DESIGN FOR TESTABILITY;

EID: 0036446083     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2002.1041832     Document Type: Article

References (6)

1. M. Hirech, J. Beausang and X. Gu, "A New Approach To Scan Chain Reordering Using Physical Design Information", proc. of ITC 1998.
2. S. Makar, "A Layout-Based Approach for Ordering Scan Chain Flip-Flop", proc. of ITC 1998.
3. Y. Konno, K. Nakamura, T. Bitoh, K. Saga, and S. Yano, "A consistent Scan Design System for Large-Scale ASICs", proc. of 10th Compendium of Papers from Asian Test Symposium, pp. 163-168, 2001.
4. Test Compiler Reference Manual. Release 2001.08, Synopsys Inc. Mountain View, CA, 2001.
5. J. Beausang, C. Ellingham, and M. Robinson, "Integrating Scan Into Hierarchical Synthesis Methodologies", proc. of ITC 1996.
6. H. Zhou, N. Shenoy and W. Nicholls, "Efficient Rectilinear Minimum Spanning Tree", Synopsys conference, 1999.