Impact of body bias on alpha- and neutron-induced soft error rates of flip-flops

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 324-325

  Karnik, Tanay ^a   Tschanz, James ^a   Bloechel, Bradley ^a   Hazucha, Peter ^a   Armstrong, Pat ^a   Narendra, Siva ^a   Keshavarzi, Ali ^a   Soumyanath, K ^a   Dermer, Greg ^a   Maiz, Jose ^a   Borkar, Shekhar ^a   De, Vivek ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ERROR CORRECTION; ERROR DETECTION; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; NEUTRONS; PROBABILITY; TRANSISTORS;

ERROR CORRECTION TECHNIQUES (ECC); SOFT ERROR RATES (SER); STATIC MASTER SLAVE (SMS); ZERO BODY BIAS (ZBB);

FLIP FLOP CIRCUITS;

EID: 4544277308     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. T. Karnik, et al., 2001 VLSI Circuit Symposium, pp. 61-62.
2. J. Tschanz, et al., 2002 ISSCC, pp. 422-423.
3. S. Narendra et al., 2002 ISSCC, pp. 270-271.
4. L. Clark, et al., 2002 ISLPED, pp. 7-12.
5. P. Hazucha, et al., 2003 IEDM, pp 523-526.
6. Y. Tosaka, et al., IEEE TED, V45, N7, 1998.
7. S. Hareland, et al., 2001 VLSI Tech. Symposium, pp. 73-74.