Scan test data volume reduction in multi-clocked designs with safe capture technique

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 148-153

  Jain, Vishal ^a   Waicukauski, John ^a  

^a SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; DISCRETE FOURIER TRANSFORMS; FLIP FLOP CIRCUITS; INTERFACES (COMPUTER); OBSERVABILITY;

MULTI-CLOCKED DESIGNS; MULTI-SYNCHRONOUS DESIGNS; SCAN TEST DATA VOLUME REDUCTION;

TIMING CIRCUITS;

EID: 0036443109     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Bart Vermeulen and Paul Merkus, "Scan Test Techniques for Multi-synchronous Digital Circuits," Fifth International Test Synthesis Workshop (ITSW'98), 1998.
2. "Designs with Multiple Clock Domains: Avoiding Clock Skew and Reducing Pattern Count using DFT Advisor and Fast Scan," Technical White Paper, http://www.mentor.com/dft
3. "Multiple Clock Domains in Scan Circuits," Technical White Paper, http://www.atgtech.com
4. N. Sherwani, W. Khan, and M. Hossain, "Zero skew clock routing in multiple-clock synchronous systems," in Proceedings of 1992 International Conference on Computer-Aided Design, 1992.
5. "Test-Quality Comparison between Full-Scan, Partial-Scan and On-Line Techniques for a Periodic Synchronizer," in Proceedings of 12-th ProRISC, pp. 550-554, 2001.
6. TetraMAX ATPG User Guide, Software Version 2001.08, Synopsys, 2001.