H-DFT: A Hybrid DFT architecture for low-cost high quality structural testing

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 1229-1238

  Wu, David M ^a   Lin, Mike ^a   Mitra, Subhasish ^a   Kim, Kee Sup ^a   Sabbavarapu, Anil ^a   Jaber, Talal ^a   Johnson, Pete ^a   March, Dale ^a   Parrish, Greg ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DATA COMPRESSION; LOGIC DESIGN; MICROPROCESSOR CHIPS;

STRUCTURAL TESTING;

DESIGN FOR TESTABILITY;

EID: 0142246847     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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