Wave-Pipelined Multiplexed (WPM) routing for Gigascale Integration (GSI)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 8, 2005, Pages 899-909

  Joshi, Ajay Jayant ^a,b   Davis, Jeffrey Alan ^a,b  

^a IEEE   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Interconnect routing; Time division multiplexing (TDM); Wave pipelining; Wire sharing

Indexed keywords

GIGASCALE INTEGRATION (GSI); INTRACLOCK; MULTILEVEL INTERCONNECT NETWORK DESIGN SIMULATOR (MINDS); WAVE-PIPELINED MULTIPLEXED (WPM);

COMPUTER SIMULATION; HIERARCHICAL SYSTEMS; INTERCONNECTION NETWORKS; PIPELINE PROCESSING SYSTEMS; ROUTERS; TRANSISTORS;

VLSI CIRCUITS;

EID: 27144525038     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.853611     Document Type: Article

References (22)

1. J. Meindl, "Low-power microelectronics: Retrospect and prospect," Proc. IEEE, vol. 83, no. 4, pp. 619-635, Apr. 1995.
2. J. Davis, R. Venkatesan, A. Kaloyeros, M. Bylansky, S. Souri, K. Banerjee, K. Saraswat, A. Rahman, A. Reif, and J. Meindl, "Interconnect limits on gigascale integration (GSI) in the 21st century," Proc. IEEE, vol. 89, no. 4, pp. 305-324, Mar. 2001.
3. International Technology Roadmap for Semiconductors [Online]. Available: http://public.itrs.net/
4. S. Kumar, A. Jantsch, J. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani, "A network on chip architecture and design methodology," in Proc. IEEE Comp. Soc., Apr. 2002, pp. 105-112.
5. J. Liu, L.-R. Zeng, D. Pamunuwa, and H. Tenhunen, "A global wire planning scheme for network-on-chip," in Proc. ISCAS 2003, vol. 4, May 2003, pp. IV-892 -IV-895.
6. P. Bhojwani and R. Mahapatra, "Interfacing cores with on-chip packet switched networks," in Proc. VLSI Design, Jan. 2003, pp. 382-387.
7. J. Liu, M. Shen, L. Zheng, and H. Tenhunen, "System level interconnect design for network-on-chip using interconnect IPs," in Proc. IEEE/ACM Int. Workshop System Level Interconnect Prediction (SLIP), 2003, Apr. 2003. pp. 117-124.
8. K. Lahiri, A. Raghunathan, and G. Lakshminarayana, "LOTTERYBUS: A new high-performance communication architecture for system-on-chip designs," in Proc. DAC, Jun. 2001, pp. 15-20.
9. A. Joshi and J. Davis, "A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI)," in Proc. IEEE/ACM Int. Workshop on System Level Interconnect Prediction (SLIP), Feb. 2004. pp. 64-68.
10. R. Venkatesan, J. Davis, K. Bowman, and J. Meindl, "Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 12, pp. 899-912, Dec. 2001.
11. J. Davis, V. De, and J. Meindl, "A stochastic wire-length distribution for gigascale integration (GSI) - Parts I and II," IEEE Trans. Electron Dev., vol. 45, no. 3, pp. 580-597, Mar. 1998.
12. V. Deodhar and J. Davis, "Optimization for throughput performance for low power VLSI interconnects," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 3, pp. 308-318, Mar. 2005.
13. Y. Cao, C. Hu, X. Huang, A. Kahng, S. Muddu, D. Stroobandt, and D. Sylvester, "Effects of global interconnect optimizations on performance estimation of deep submicron design," in Proc ICCAD, Nov. 2000, pp. 56-61.
14. H. Bakoglu and J. Meindl, "Optimal interconnection circuits for VLSI," IEEE Trans. Electron Dev., vol. ED-32, no. 5, pp. 903-909, May 1985.
15. J. Xu and W. Wolf, "A wave-pipelined on-chip interconnect structure for network-on-chips," in Proc. HOTI, Aug. 2003, pp. 10-14.
16. R. Kumar, "Interconnect and noise immunity design for the Pentium 4 processor," in Proc. DAC, Jun. 2003, pp. 938-943.
17. H. Ando et al., "A 1.3-GHz fifth-generation SPARC64 microprocessor," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1896-1905, Nov. 2003.
18. Berkeley Predictive Technology Model (BPTM) [Online]. Available: http://www-device.eecs.berkeley.edu/~ptm/introduction.html
19. L. Carloni, K. McMillan, and A. Sangiovanni-Vincentelli, "Theory of latency insensitive design," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 20, no. 9, pp. 1059-1076, Sep. 2001.
20. M. Dall'Osso, G. Biccari, L. Giovannini, D. Bertozzi, and L. Benini, "Xpipes: A latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs," in Proc. ICCD, Oct. 2003, pp. 536-539.
21. G. Sai-Halasz, "Performance trends in high end processors," Proc. IEEE, vol. 83, no. 1, pp. 18-34, Jan. 1995.
22. H. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Reading, M.A: Addison-Wesley, 1990.