A 2-slot Time-Division Multiplexing (TDM) interconnect network for Gigascale Integration (GSI)

International Workshop on System Level Interconnect Prediction, SLIP

Volumn , Issue , 2004, Pages 64-68

  Joshi, Ajay ^a   Davis, Jeff ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Interconnect area; Time division multiplexing; Wire sharing

Indexed keywords

CIRCUIT THEORY; ELECTRIC WIRE; SILICON; SWITCHING; TELECOMMUNICATION REPEATERS; TIME DIVISION MULTIPLEXING;

GIGASCALE INTEGRATION (GSI); INTERCONNECT AREA; SYSTEM-ON-CHIP (SOC); WIRE SHARING;

VLSI CIRCUITS;

EID: 19544379531     PISSN: None     EISSN: 15445631     Source Type: Conference Proceeding    
DOI: 10.1145/966759.966761     Document Type: Conference Paper

References (12)

1. http://public.itrs.net/
2. J. D. Meindl, "Low-power microelectronics: Retrospect and prospect," Proc. IEEE, vol.83, pp. 619-635, Apr.1995.
3. st century," Proc. IEEE, vol.89, pp. 305-324, March 2001
4. V. V. Deodhar and J. A. Davis, "Voltage scaling and repeater insertion for high throughput low power interconnects," Proc. ISCAS 2003, vol.5, pp. V-349-V-352, May 2003
5. S. Kumar, A. Jantsch, J. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja and A. Hemani, "A Network on Chip Architecture and Design Methodology," Proc. IEEE Comp Soc, pp. 105-112, April 2002
6. J. Liu, L-R. Zeng, D. Pamunuwa and H. Tenhunen, "A Global Wire Planning Scheme for Network-on-Chip," Proc. ISCAS 2003, vol.4, pp IV-892-IV-895, May 2003
7. P. Bhojwani and R. Mahapatra, "Interfacing cores with on-chip packet switched networks," Proc. VLSI design, pp. 382-387, Jan. 2003
8. P. Zarkesh-Ha, K. Doniger, W. Loh and P. Wright, "Prediction of Interconnect Pattern Density Distribution: Derivation, Validation and Applications," Proc. SLIP, pp. 85-91, Apr. 2003
9. R. Venkatesan, J. A. Davis, K. A. Bowman and J. D. Meindl, "Optimal n-tier Multilevel Interconnect Architectures for Gigascale Integration (GSI)," IEEE Trans. VLSI systems, vol. 9, pp. 899-912, Dec. 2001
10. J. A. Davis, V. K. De and J. D. Meindl, "A stochastic wire-length distribution for gigascale integration (GSI)-Parts I and II," IEEE Trans. Electron Dev., vol.45, pp. 580-597, Mar. 1998
11. G. A. Sai-Halasz, "Performance trends in high end processors," Proc. IEEE, vol.83, pp. 18-34, Jan. 1995
12. H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Reading, M.A: Addison-Wesley, 1990