Interconnect and noise immunity design for the Pentium® processor

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 938-943

  Kumar, Rajesh ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Design

Indexed keywords

CAPACITANCE; COMPUTER AIDED DESIGN; INDUCTANCE; SPURIOUS SIGNAL NOISE; TELECOMMUNICATION REPEATERS;

INTERCONNECT DELAY;

MICROPROCESSOR CHIPS;

EID: 0043136430     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Rajesh Kumar, Eitan Zahavi, Desmond Kirkpatrick, "Accurate design and analysis of Noise Immunity for high-performance circuit design" Design and Test Technology Conference (DTTC) 1997. Intel internal document.
2. K.L. Shepard et.al. "Harmony: static noise analysis of deep submicron digital integrated circuits" Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Volume: 18 Issue: 8, Aug 1999
3. Eitan Zahavi, Rajesh Kumar et. al., "Novel Methodology and Tools for Noise Immunity Design and Verification," DTTC 1998. Intel internal document.
4. Madhu Swarna et. al., "Integrated timing and noise characterization of sequentials for accuracy and increased design space," DTTC 2000. Intel internal document.
5. Conley, Kirkpatrick et. al., DTTC 1995. Intel internal document.