System Level Interconnect Design for Network-on-Chip Using Interconnect IPs

International Workshop on System Level Interconnect Prediction

Volumn , Issue , 2003, Pages 117-124

  Liu, Jian ^a   Shen, Meigen ^a   Zheng, Li Rong ^a   Tenhunen, Hannu ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

Bandwidth optimization; Interconnect; Interconnect IP; Network on chip

Indexed keywords

APPROXIMATION THEORY; BANDWIDTH; COMPUTER SIMULATION; DATA COMMUNICATION SYSTEMS; INTELLECTUAL PROPERTY; INTERFACES (COMPUTER); MULTIPLEXING; NANOTECHNOLOGY; OPTIMIZATION; SYSTEMS ANALYSIS;

INTERCONNECT INTELLECTUAL PROPERTY; NETWORK ON CHIP;

INTERCONNECTION NETWORKS;

EID: 1442352349     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/639952.639953     Document Type: Conference Paper

References (13)

1. Dally W. J. and B. Towles. Route Packets, Not Wires: On-Chip Interconnection Networks. Design Automation Conference, 2001, Proceedings, 684-689.
2. Goossens K. Guaranteeing the Quality of Services in Network on Chip. Chapter 4 in "Network on Chip", Kluwer (March 2003). http://www.dcs.ed.ac.uk/home/kgg/2003-networksonchip-chap4.pdf
3. Guerrier P. and Greiner A. A Generic Architecture for On-Chip Packet-Switched Interconnections. Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings, 2000,250-256.
4. Ho R, Mai K. W. and Horowitz M. The Future of Wires. Proceedings of The IEEE, vol. 89, no. 4 (April 2001).
5. Hemani A., Jantsch A., Kumar S., Postula A., Öberg J., Millberg M. and Lindqvist D. Network on Chip: An Architecture for Billion Transistor Era. Proceeding of the IEEE NorChip Conference (November 2000).
6. Jantsch Axel. Network on Chip. Proceedings of the Conference Radio vetenskap och Kommunication, Stockholm (June 2002).
7. Kurose J. F., Ross K. W. Computer Networking: A Top-Down Approach Featuring the Internet. Addison Wesley Longman, Inc (2001).
8. Maheshwari A., Srinivasaraghavan S. and Burleson W. Quantifying the Impact of Current-Sensing on Interconnect Delay Trends. ASIC/SOC Conference, 2002. 15th Annual IEEE International (2002), 461-465.
9. Nilsson E. Design and Implementation of a Hot-potato Switch in Network on Chip. Master of Science thesis, Laboratory of Electronics and Computer Systems, Royal Institute of Technology (KTH), Sweden (June 2002).
10. Pamunuwa D., Zheng L-R. and Tenhunen H. Optimising Bandwidth Over Deep Sub-micron Interconnect. Proc. of the 2002 IEEE International Symposium on Circuits And Systems (ISCAS), Scottsdale, Arizona, USA (May 2002).
11. Tenhunen H. Workshop "Systems on Chip, Systems in Package", ESSCIRC 2001, Villach Austria (Sep 2001).
12. Zheng L-R. Design, Analysis and Integration of Mixed-Signal Systems for Signal and Power Integrity. PhD thesis, Laboratory of Electronics and Computer Systems, Royal Institute of Technology (KTH), Sweden (2001).
13. Zheng L-R. Design and Analysis of Power Integrity in Deep Submicron System-on-Chip Circuits. Analog Integrated Circuits and Signal Processing, 30, 2002, 15-29.