Optimization of throughput performance for low-power VLSI interconnects

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 3, 2005, Pages 308-318

  Deodhar, Vinita V ^a   Davis, Jeffrey A ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

High throughput; Interconnect performance; Low power; Repeater insertion; Wave pipelining

Indexed keywords

ELECTRIC POTENTIAL; ELECTRIC POWER SYSTEM INTERCONNECTION; ENERGY DISSIPATION; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; THROUGHPUT; TRANSISTORS; VOLTAGE CONTROL; WIRE PRODUCTS;

HIGH THROUGHPUT; INSERTION; INTERCONNECT PERFORMANCE; LOW POWER; REPEATER; WAVE PIPELINING;

VLSI CIRCUITS;

EID: 15844415671     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.842898     Document Type: Article

References (11)

1. (2002) International technology roadmap for semiconductors (ITRS). [Online]. Available: http://public.itrs.net
2. J. A. Davis et al., "Interconnect limits on gigascale integration (GSI) in the 21st century," Proc. IEEE, vol. 89, no. Mar., pp. 305-324, 2001.
3. H. Shah, P. Shiu, B. Bell, M. Aldredge, N. Sopory, and J. A. Davis, "Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects," in Proc. IEEE Int. Conf. Computer-Aided Design, 2002, pp. 280-284.
4. MOSIS. The MOSIS Service for HSPICE Models. [Online]. Available: http://www.mosis.org
5. Y. I. Ismail and E. G. Friedman, "Effects of inductance on the propagation delay and repeater insertion in VLSI circuits," in Proc. 36th ACM IEEE Design Autom. Conf., 1999, pp. 721-724.
6. T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's," IEEE Trans. Electron Devices, vol. 40, pp. 118-124, Jan. 1993.
7. W. Liu, MOSFET Models for SPICE Simulation, Including BSIM3v3 and BSIM4. New York: Wiley, 2001, pp. 31-33.
8. 2 SRAM cell," in IEDM Tech. Dig., 2002, pp. 61-64.
9. H. B. Bakoglu and J. D. Meindl, "Optimal interconnection circuits for VLSI," IEEE Trans. Electron Devices, vol. ED-32, pp. 903-909, May 1985.
10. J. A. Butts and G. S. Sohi, "A static power model for architects," in Proc. IEEE/ACM 33rd Annu. Int. Symp. Microarchitecture, 2000, pp. 191-201.
11. A. B. Kahng and S. Muddu, "Optimal equivalent circuits for interconnect delay calculations using moments," in Proc. Eur. Design Autom. Conf., 1994, pp. 164-169.