Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO2 gate stack with low preexisting traps

IEEE Electron Device Letters

Volumn 26, Issue 9, 2005, Pages 610-612

  Sa, N ^a   Kang, J F ^a   Yang, H ^a   Liu, X Y ^a   He, Y D ^a   Han, R Q ^a   Ren, C ^b   Yu, H Y ^c   Chan, D S H ^b   Kwong, D L ^d  

^a PEKING UNIVERSITY   (China)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c IMEC   (Belgium)

^d The University of Texas at Austin   (United States)

Author keywords

Electric stress induced defect generation (ESIDG); High gate dielectric; Positive bias temperature instability (PBTI); Reaction diffusion (R D) model

Indexed keywords

ACTIVATION ENERGY; DIELECTRIC MATERIALS; MATHEMATICAL MODELS; TEMPERATURE; THERMAL STRESS; THERMODYNAMIC STABILITY; THRESHOLD VOLTAGE;

ELECTRIC STRESS INDUCED DEFECT GENERATION (ESIDG); POSITIVE BIAS TEMPERATURE INSTABILITY (PBTI); REACTION-DIFFUSION MODEL;

GATES (TRANSISTOR);

EID: 26444468109     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2005.853683     Document Type: Article

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