-
1
-
-
0029536659
-
Cost-Effective generation of minimal test sets for stuck-at Faults in combinational logic circuits
-
Dec.
-
S. Kajihara, I. Pomeranz, K. Kinoshita and S. M. Reddy, "Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits," IEEE Trans. CAD. , Vol. 14, No. 12, pp. 1496-1504, Dec. 1995.
-
(1995)
IEEE Trans. CAD.
, vol.14
, Issue.12
, pp. 1496-1504
-
-
Kajihara, S.1
Pomeranz, I.2
Kinoshita, K.3
Reddy, S.M.4
-
2
-
-
0032320384
-
Test set compaction algorithms for combinational circuits
-
Nov.
-
I. Hamzaoglu and J. H. Patel, "Test Set Compaction Algorithms for Combinational Circuits," ICCAD, pp. 283-288, Nov. 1998.
-
(1998)
ICCAD
, pp. 283-288
-
-
Hamzaoglu, I.1
Patel, J.H.2
-
3
-
-
0032318593
-
Built-in self testing of sequential circuits using precomputed test sets
-
V. Iyengar, K. Chakrabarty, and B. T. Murray, "Built-in Self Testing of Sequential Circuits Using Precomputed Test Sets," 16th VLSI Test Symposium, pp. 418-423, 1998.
-
(1998)
16th VLSI Test Symposium
, pp. 418-423
-
-
Iyengar, V.1
Chakrabarty, K.2
Murray, B.T.3
-
4
-
-
0032682922
-
Scan vector compression/decompression using statistical coding
-
April
-
A. Jas, J. Ghosh-Dastidar, and N. A. Tuba, "Scan Vector Compression/Decompression Using Statistical Coding," VLSI Test Symposium, pp. 114-120, April 1999.
-
(1999)
VLSI Test Symposium
, pp. 114-120
-
-
Jas, A.1
Ghosh-Dastidar, J.2
Tuba, N.A.3
-
5
-
-
0033741842
-
Test data compression for system-on-a-Chip using golomb codes
-
April
-
A. Chandra and K. Chakrabarty, "Test Data Compression for System-on-a-Chip Using Golomb Codes," VLSI Test Symposium, pp. 113-120, April 2000.
-
(2000)
VLSI Test Symposium
, pp. 113-120
-
-
Chandra, A.1
Chakrabarty, K.2
-
6
-
-
0033898948
-
Test transformation to improve compaction by statistical encoding
-
Jan.
-
H. Ichihara, K. Kinoshita, I. Pomeranz, S. M. Reddy, "Test Transformation to Improve Compaction by Statistical Encoding," International Conf. on VLSI Design, pp. 294-299, Jan. 2000.
-
(2000)
International Conf. on VLSI Design
, pp. 294-299
-
-
Ichihara, H.1
Kinoshita, K.2
Pomeranz, I.3
Reddy, S.M.4
-
7
-
-
0035704290
-
A smart BIST variant guarnteed encoding
-
Nov.
-
B. Koenemann, et. al. , "A Smart BIST Variant Guarnteed Encoding," 10th Asian Test Symposium, pp. 325-330, Nov. 2001.
-
(2001)
10th Asian Test Symposium
, pp. 325-330
-
-
Koenemann, B.1
-
8
-
-
0029252184
-
Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers
-
February
-
S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, "Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers," IEEE Trans. Computers, vol. 44, pp. 223-233, February 1995.
-
(1995)
IEEE Trans. Computers
, vol.44
, pp. 223-233
-
-
Hellebrand, S.1
Rajski, J.2
Tarnick, S.3
Venkataraman, S.4
Courtois, B.5
-
9
-
-
0035687722
-
Two-Dimensional test data compression for scan-Based deterministic BIST
-
Oct.
-
H. Liang, S. Hellebrand, H.-J. Wunderlich, "Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST," International Test Conf. , pp. 894-902, Oct. 2001.
-
(2001)
International Test Conf.
, pp. 894-902
-
-
Liang, H.1
Hellebrand, S.2
Wunderlich, H.-J.3
-
10
-
-
0035684018
-
Test vector encoding using partial LFSR Reseeding
-
Oct.
-
C. V. Krishna, A. Jas, and N. A. Touba, "Test Vector Encoding Using Partial LFSR Reseeding," International Test Conf. , pp. 885-893, Oct. 2001.
-
(2001)
International Test Conf.
, pp. 885-893
-
-
Krishna, C.V.1
Jas, A.2
Touba, N.A.3
-
11
-
-
0034848095
-
Test volume and application time reduction through scan chain concealment
-
June
-
I. Bayraktaroglu, and A. Orailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment," Design Automation Conf. , pp. 151-155, June 2001.
-
(2001)
Design Automation Conf.
, pp. 151-155
-
-
Bayraktaroglu, I.1
Orailoglu, A.2
-
13
-
-
0032306324
-
-
ICCAD-98 Nov.
-
K. Lee, J. Chen, and C. Huang, "Using a Single Input to Support Multiple Scan Chains," ICCAD-98, pp. 74-78, Nov. 1998.
-
(1998)
Using A Single Input to Support Multiple Scan Chains
, pp. 74-78
-
-
Lee, K.1
Chen, J.2
Huang, C.3
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