Billion-transistor architectures: There and back again

Computer

Volumn 37, Issue 3, 2004, Pages 22-28

  Burger, Doug ^a   Goodman, James R ^b  

^a University of Texas at Austin   (United States)

^b UNIVERSITY OF AUCKLAND   (New Zealand)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER GRAPHICS; COMPUTER HARDWARE; COMPUTER SOFTWARE; DYNAMIC RANDOM ACCESS STORAGE; INTERFACES (COMPUTER); MULTIMEDIA SYSTEMS; PARALLEL PROCESSING SYSTEMS; PROGRAM COMPILERS; REDUCED INSTRUCTION SET COMPUTING; SERVERS; TRANSISTORS; VIRTUAL REALITY;

BILLION-TRANSISTOR ARCHITECTURES; DATA PARALLELISM; INSTRUCTION-LEVEL PARALLELISM; INTERFILE COMMUNICATION;

COMPUTER ARCHITECTURE;

EID: 1842425453     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/MC.2004.1273999     Document Type: Article

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