Walk-time techniques: Catalyst for architectural change

Computer

Volumn 30, Issue 9, 1997, Pages 40-42

  Fisher, Joseph A ^a,b,c  

^a HEWLETT PACKARD LABORATORIES   (United States)

^b NEW YORK UNIVERSITY   (United States)

^c IEEE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPUTER ARCHITECTURE; PROGRAM TRANSLATORS;

LEGACY SOFTWARE; WALK TIME TECHNIQUES;

PROGRAM COMPILERS;

EID: 0031237815     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.612246     Document Type: Article

References (4)

1. R. Lee, "Accelerating Multimedia with Enhanced Microprocessors," IEEE Micro, Apr. 1995, pp. 22-32.
2. R. Sites et al., "Binary Translation," Digital Tech. J., Vol. 4, No. 4, 1992.
3. D. Wall, "Global Register Allocation at Link-Time," Proc. Symp. Compiler Construction, ACM Press, New York, 1986, pp. 264-275.
4. K. Pettis and R. Hansen, "Profile Guided Code Positioning," Proc. Programming Language Design and Implementation, ACM Press, New York, 1990, pp. 16-27.