On-chip transparent wire pipelining

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 160-167

  Casu, Mario R ^a   Macchiarulo, Luca ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

DATA REDUCTION; ELECTRIC WIRE; INTELLECTUAL PROPERTY; NETWORK PROTOCOLS; SEMICONDUCTOR COUNTERS; THROUGHPUT;

CLOCK FREQUENCY; INTERCONNECTION DELAY; SYSTEM-ON-CHIP (SOC); WIRE PIPELINING (WP);

INTEGRATED CIRCUIT LAYOUT;

EID: 17644381663     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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