Issues in implementing latency insensitive protocols

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 1390-1391

  Casu, Mario R ^a   Macchiarulo, Luca ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

FEEDFORWARD TOPOLOGY; LATENCY INSENSITIVE PROTOCOLS (LIP); PATH EQUALIZATION; SYSTEMS ON CHIP (SOC); FUNCTIONAL MODULES; LATENCY-INSENSITIVE DESIGNS; RELAY STATIONS;

COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; DATA TRANSFER; INTERCONNECTION NETWORKS; SIGNAL PROCESSING; EXHIBITIONS;

MICROPROCESSOR CHIPS; DESIGN;

EID: 3042522756     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269102     Document Type: Conference Paper

References (5)

1. L.P. Carloni et al., Theory of Latency-Insensitive Design, IEEE TCAD, vol. 20, No. 9, Sept. 2001, pp. 1059-1076.
2. L.P. Carloni et al., A Methodology for "Correct-by- Construction" Latency Insensitive Design", Proc. ICCAD 99, pp. 309-315.
3. M.R. Casu and L. Macchiarulo, A Detailed Implementation of Latency Insensitive Protocols, Proc. FMGALS 2003, Pisa, Italy, Sep. 2003. Available at http://www.vlsilab.polito.it/~casu
4. K.L. McMillan, "Getting Started with SMV," Cadence Berkely Labs, 2001 Addison St., Berkely, CA, March 1999.
5. L.P. Carloni and A.L. Sangiovanni-Vincentelli, Performance Analysis and Optimization of Latency Insensitive Protocols, Proc. DAC 00, pp. 361-367.