A method for correcting the functionality of a wire-pipelined circuit

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 570-575

  Nookala, Vidyasagar ^a   Sapatnekar, Sachin S ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

Synchronous design; Wire pipelining

Indexed keywords

BENCHMARKING; CLOCKS; FLIP FLOP CIRCUITS; MICROPROCESSOR CHIPS; OPTIMIZATION; SYNCHRONIZATION; WIRE;

CLOCK FREQUENCIES; SYNCHRONOUS DESIGN; WIRE PIPELINING;

INTEGRATED CIRCUIT LAYOUT;

EID: 4444361440     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996724     Document Type: Conference Paper

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