Retiming for Wire Pipelining in System-On-Chip

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 215-220

  Lin, Chuan ^a   Zhou, Hai ^a  

^a Northwestern University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK DELAY; WIRE PIPELINING;

ALGORITHMS; COMPUTATIONAL COMPLEXITY; FLIP FLOP CIRCUITS; GATES (TRANSISTOR); MATHEMATICAL MODELS; OPTIMIZATION; POLYNOMIALS; RANDOM ACCESS STORAGE; THEOREM PROVING; TOPOLOGY;

MICROPROCESSOR CHIPS;

EID: 0346778788     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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