Architecture-level synthesis for automatic interconnect pipelining

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 602-607

  Cong, Jason ^a   Fan, Yiping ^a   Zhang, Zhiru ^a  

^a Engineering IV   (United States)

Author keywords

High level synthesis; Interconnect pipelining; Multi cycle communication; Register binding; Scheduling

Indexed keywords

AUTOMATION; CLOCKS; COMMUNICATION SYSTEMS; LOGIC DESIGN; PRODUCT DESIGN; SCHEDULING; SYNCHRONIZATION;

AUTOMATIC SYNTHESIS; INTERCONNET PIPELINING; MULTI-CYCLE COMMUNICATION; RESISTER BINDING;

NANOTECHNOLOGY;

EID: 4444250755     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996731     Document Type: Conference Paper

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