Simultaneous power supply planning and noise avoidance in floorplan design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 4, 2005, Pages 578-586

  Chen, Hung Ming ^a   Huang, Li Da ^b   Liu, I Min ^c   Wong, Martin D F ^d  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b TEXAS INSTRUMENTS   (United States)

^c CADENCE DESIGN SYSTEMS   (United States)

^d University of Illinois at Urbana Champaign   (United States)

Author keywords

Floorplanning; Physical design; Power supply planning; Signal integrity

Indexed keywords

BANDWIDTH; CONSTRAINT THEORY; COST EFFECTIVENESS; ELECTRIC POWER SUPPLIES TO APPARATUS; MICROPROCESSOR CHIPS; PLANNING; RELIABILITY; SPURIOUS SIGNAL NOISE;

NETWORK DESIGN; SIGNAL INTEGRITY; VOLTAGE FLUCTUATIONS; WIRE-BONDED TECHNOLOGY;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 16444381153     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.844088     Document Type: Article

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