Simultaneous floorplanning and buffer block planning

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2003-January, Issue , 2003, Pages 431-434

  Hui Ru Jiang, I ^a   Chang, Yao Wen ^b   Jou, Jing Yang ^c   Chao, Kai Yuan ^d  

^a VIA Technologies Inc   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^c NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^d INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER BLOCK PLANNING; DESIGN CONVERGENCE; FLOOR-PLANNING; INTERCONNECT DELAY; INTERCONNECT OPTIMIZATION; TECHNOLOGY ADVANCES; TIMING CLOSURES;

COMPUTER AIDED DESIGN;

EID: 0042192063     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195054     Document Type: Conference Paper

References (13)

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