Methodology for I/O cell placement and checking in ASIC designs using area-array power grid

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2000, Pages 125-128

  Buffet, Patrick H ^a   Natonio, Joseph ^a   Proctor, Robert A ^a   Sun, Yu H ^a   Yasar, Gulsun ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; ELECTROMIGRATION; LOGIC CIRCUITS;

AREA ARRAY POWER GRID; ELECTRICAL RULE CHECKING; I-O CELL PLACEMENT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033725306     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)