Floorplan-based planning methodology for power and clock distribution in ASICs

Proceedings - Design Automation Conference

Volumn , Issue , 1999, Pages 766-771

  Yim, Joon Seo ^a   Bae, Seong Ok ^a   Kyung, Chong Min ^a  

^a LG   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; PARAMETER ESTIMATION; TIMING CIRCUITS;

CLOCK BUFFERS; CLOCK INTERCONNECT SIZING; GATE-LEVEL NETLIST;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0032690819     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (17)