Layout Techniques for Minimizing On-Chip Interconnect Self Inductance

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 566-571

  Massoud, Yehia ^a   Majors, Steve ^b   Bustami, Tareq ^b   White, Jacob ^a  

^a USA   (United States)

^b MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTROMAGNETIC FIELDS; INDUCTANCE; MICROSTRIP LINES; ELECTRIC NETWORK TOPOLOGY; ELECTROMAGNETIC FIELD EFFECTS; INTEGRATED CIRCUIT LAYOUT; SENSITIVITY ANALYSIS;

ELECTROMAGNETIC FIELD SOLVER; ELECTROSTATIC EFFECT; GROUND PLANES; INTERCONNECT LINES; INTERCONNECT TOPOLOGY; MAGNETIC EFFECTS; ON CHIP INTERCONNECT; SIGNAL LINES;

INTEGRATED CIRCUIT INTERCONNECTS; MICROPROCESSOR CHIPS;

SELF-INDUCTANCE;

EID: 0031623454     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/277044.277194     Document Type: Conference Paper

References (7)

1. L. Pileggi, "Coping with RC(L) Interconnect Design Headaches, " Proceedings of the International Conference on Computer-Aided Design, October, 1995.
2. D.A. Priore, "Inductance on Silicon for Sub-Micron CMOS VLSI, " IEEE Symposium on VLSI Circuits, 1993.
3. Y. Massoud and J. White, "Simulation and Modeling of the Effect of Substrate Conductivity on Coupling Inductance, " Proceedings of the International Electron Devices Meeting, Washington, DC, pp. 491-494, December 1995.
4. M. Kamon, M. Tsuk, arid J. White "FASTHENRY: A Multipole-Accelerated 3-D Inductance Extraction Program, " IEEE Trans. on MTT, vol. 42, No. 9, pp. 1750-1758, September 1994.
5. R. Harrington, Field Computations by Moment Methods. New York: Macldillan, 1968.
6. L. Greengard, The Rapid Evaluation of Potential Fields in Particle Systems. Cambridge, Massachusetts: M.I.T. Press, 1988.
7. K. Nabors and J. White, "FastCap: A Multipole-Accelerated 3-D Capacitance Extraction Program, " IEEE Transactions on Computer-Aided Design, 1447-1459, November 1991.