Reduction of interconnect delay by exploiting cross-talk

European Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 301-304

  Van Dijk, S ^a   Hely, D ^b  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b UNIVERSITÉ DE LYON   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; DELAY REDUCTION; INTERCONNECT DELAY; REPEATER INSERTION; SIGNAL INTEGRITY; SPATIAL POSITIONS; TRAVELLING WAVES; WIRE DELAYS;

CMOS INTEGRATED CIRCUITS; CROSSTALK; INTERCONNECTION NETWORKS;

WIRE;

EID: 84893639086     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Masahiro Nomura, US Patent No. 6,128,347, Oct. 2000.
2. Norman Kojima, Masataka Matsui, et al.,"Repeater Insertion Method and its Application to a 300 MHz 128-bit 2-way Superscalar Microprocessor", Proceedings ASP-DAQ 2000, pp. 641-646.
3. I-Min Liu, Adnan Aziz and D.F. Wong, "Meeting Delay Constraints in DSM by Minimal Repeater Insertion", Proceedings DATE, 2000, pp. 436-440.
4. Samuel Naffziger, "Designing Circuits for Interconnect", IEEE ISSCC multi-ghz processors workshop, 2000.
5. Jason Cong, Lei He, Cheng-Kok Koh and Zhigang Pan, "Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance", IEEE/ACM ICCAD, 1997, pp. 139-146..
6. H.J.M. Veendrick, "From Basisc to Asics", Kluwer Academic Publishers, Dordrecht, second edition, 2000, pp. 433-434.
7. L. Vandenberghe et al, "Optimizing Dominant Time Constant in RC Circuits", IEEE Trans. Computer-Aided Design, vol. 17, no. 2, pp. 110-125, Feb. 1998.
8. Charles J. Alpert, Anirudh Devgan, et al., "Interconnect Synthesis Without Wire Tapering", IEEE Trans. Computer-Aided Design, vol. 20, no.l, pp. 90-104, Jan. 2000.