-
1
-
-
0036901928
-
"LP/LV ratioed DG-SOI logic with (intrinsically on) symmetric DG-MOSFET load"
-
S. Mitra, A. Salman, D. P. Ioannou, and D. E. Ioannou, "LP/LV ratioed DG-SOI logic with (intrinsically on) symmetric DG-MOSFET load," in Proc. IEEE Int. SOI Conf., 2002, pp. 66-67.
-
(2002)
Proc. IEEE Int. SOI Conf.
, pp. 66-67
-
-
Mitra, S.1
Salman, A.2
Ioannou, D.P.3
Ioannou, D.E.4
-
2
-
-
0142185837
-
"Low voltage/low power sub 50 nm double gate SOI ratioed logic"
-
S. Mitra, A. Salman, D. P. Ioannou, C. Tretz, and D. E. Ioannou, " Low voltage/low power sub 50 nm double gate SOI ratioed logic," in Proc. IEEE Int. SOI Conf., 2003, pp. 177-178.
-
(2003)
Proc. IEEE Int. SOI Conf.
, pp. 177-178
-
-
Mitra, S.1
Salman, A.2
Ioannou, D.P.3
Tretz, C.4
Ioannou, D.E.5
-
3
-
-
0035714368
-
"Triple-self-aligned, planar double-gate MOSFETs: Devices and circuits"
-
K. W. Guarini, P. M. Solomon, Y. Zhang, K. K. Chan, E. C. Jones, G. M. Cohen, A. Krasnoperova, M. Ronay, O. Dokumaci, J. J. Bucchignano, C. Cabral Jr., C. Lavoie, V. Ku, D. C. Boyd, K. S. Petrarca, I. V. Babich, J. Treichler, and P. M. Kozlowski, "Triple-self-aligned, planar double-gate MOSFETs: devices and circuits," in IEDM Tech. Dig., 2001, pp. 425-428.
-
(2001)
IEDM Tech. Dig.
, pp. 425-428
-
-
Guarini, K.W.1
Solomon, P.M.2
Zhang, Y.3
Chan, K.K.4
Jones, E.C.5
Cohen, G.M.6
Krasnoperova, A.7
Ronay, M.8
Dokumaci, O.9
Bucchignano, J.J.10
Cabral Jr., C.11
Lavoie, C.12
Ku, V.13
Boyd, D.C.14
Petrarca, K.S.15
Babich, I.V.16
Treichler, J.17
Kozlowski, P.M.18
-
4
-
-
0142154823
-
"A low power four transistor Schmitt Trigger for asymmetric double gate fully depleted SOI devices"
-
T. Cakici, A. Bansal, and K. Roy, "A low power four transistor Schmitt Trigger for asymmetric double gate fully depleted SOI devices," in Proc. IEEE Int. SOI Conf., 2003, pp. 21-22.
-
(2003)
Proc. IEEE Int. SOI Conf.
, pp. 21-22
-
-
Cakici, T.1
Bansal, A.2
Roy, K.3
-
5
-
-
0033682013
-
"DC and AC performance analysis of 25 nm symmetric/asymmetric double-gate, back-gate and bulk CMOS"
-
M. Ieong, H.-S. P. Wong, Y. Taur, P. Oldiges, and D. J. Frank, "DC and AC performance analysis of 25 nm symmetric/asymmetric double-gate, back-gate and bulk CMOS," in Proc. SISPAD, 2000, pp. 147-150.
-
(2000)
Proc. SISPAD
, pp. 147-150
-
-
Ieong, M.1
Wong, H.-S.P.2
Taur, Y.3
Oldiges, P.4
Frank, D.J.5
-
6
-
-
0032284102
-
"Device design considerations for double-gate, ground-plane, and single-gated ultrathin SOI MOSFETs at the 25-nm channel length generation"
-
H.-S. P. Wong, D. J. Frank, and P. M. Solomon, "Device design considerations for double-gate, ground-plane, and single-gated ultrathin SOI MOSFETs at the 25-nm channel length generation," in IEDM Tech. Dig., 1998, pp. 407-410.
-
(1998)
IEDM Tech. Dig.
, pp. 407-410
-
-
Wong, H.-S.P.1
Frank, D.J.2
Solomon, P.M.3
-
7
-
-
0034171745
-
"Substrate crosstalk suppression capability of silicon-on-insulator substrates with buried ground planes (GPSOI)"
-
Apr
-
J. S. Hamel, S. Stefanou, M. Bain, B. M. Armstrong, and H. S. Gamble, "Substrate crosstalk suppression capability of silicon-on-insulator substrates with buried ground planes (GPSOI)," IEEE Microwave Guided Wave Lett., vol. 10, pp. 134-135, Apr. 2000.
-
(2000)
IEEE Microwave Guided Wave Lett.
, vol.10
, pp. 134-135
-
-
Hamel, J.S.1
Stefanou, S.2
Bain, M.3
Armstrong, B.M.4
Gamble, H.S.5
-
8
-
-
0346499659
-
"Back-gated MOSFET's with controlled silicon thickness for adaptive threshold-voltage control"
-
Jan
-
U. Avci and S. Tiwari, "Back-gated MOSFET's with controlled silicon thickness for adaptive threshold-voltage control," Electron. Lett. vol. 40, pp. 74-75, Jan. 2004.
-
(2004)
Electron. Lett.
, vol.40
, pp. 74-75
-
-
Avci, U.1
Tiwari, S.2
-
9
-
-
0038528639
-
"Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors"
-
May
-
J. W. Tschanz, S. Narendra, R. Nair, and V. De, "Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors," IEEE J. Solid-State Circuits, vol. 38, pp. 826-829, May 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, pp. 826-829
-
-
Tschanz, J.W.1
Narendra, S.2
Nair, R.3
De, V.4
-
10
-
-
0036858210
-
"Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage"
-
Nov
-
J. W. Tschanz, J. T. Kao, S. G. Narendra, R. Nair, D. A. Antoniadis, A. P. Chandrakasan, and V. De, "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," IEEE J. Solid-State Circuits, vol. 37, pp. 1396-1402, Nov. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, pp. 1396-1402
-
-
Tschanz, J.W.1
Kao, J.T.2
Narendra, S.G.3
Nair, R.4
Antoniadis, D.A.5
Chandrakasan, A.P.6
De, V.7
-
11
-
-
0030087383
-
"Dependence of current match on back-gate bias in weakly inverted MOS transistors and its modeling"
-
Feb
-
M.-J. Chen, J.-S. Ho, and T.-H. Huang, "Dependence of current match on back-gate bias in weakly inverted MOS transistors and its modeling," IEEE J. Solid-State Circuits, vol. 31, pp. 259-262, Feb. 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, pp. 259-262
-
-
Chen, M.-J.1
Ho, J.-S.2
Huang, T.-H.3
-
12
-
-
0035336163
-
"Body bias dependence of 1/f noise in nMOS transistors from deep-subthreshold to strong inversion"
-
May
-
N. Park and K. O. Kenneth, "Body bias dependence of 1/f noise in nMOS transistors from deep-subthreshold to strong inversion," IEEE Trans. Electron Devices, vol. 48, pp. 999-1001, May 2001.
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, pp. 999-1001
-
-
Park, N.1
Kenneth, K.O.2
-
13
-
-
0029404107
-
"Application of the back gate in MOS weak inversion translinear circuits"
-
Nov
-
J. Mulder, A. C. van der Woerd, W. A. Serdijn, and A. H. M. van Roermund, "Application of the back gate in MOS weak inversion translinear circuits," IEEE Trans. Circuits Syst. I, vol. 42, no. 11, pp. 958-962, Nov. 1995.
-
(1995)
IEEE Trans. Circuits Syst. I
, vol.42
, Issue.11
, pp. 958-962
-
-
Mulder, J.1
van der Woerd, A.C.2
Serdijn, W.A.3
van Roermund, A.H.M.4
-
14
-
-
0030164323
-
"Back-gate forward bias method for low-voltage CMOS digital circuits"
-
June
-
M.-J. Chen, J.-S. Ho, T.-H. Huang, C.-H. Yang, Y.-N. Jou, and T. Wu, "Back-gate forward bias method for low-voltage CMOS digital circuits," IEEE Trans. Electron Devices, vol. 43, pp. 904-910, June 1996.
-
(1996)
IEEE Trans. Electron Devices
, vol.43
, pp. 904-910
-
-
Chen, M.-J.1
Ho, J.-S.2
Huang, T.-H.3
Yang, C.-H.4
Jou, Y.-N.5
Wu, T.6
-
15
-
-
0036905779
-
"Effect of back-gate biasing on the performance and leakage control in deeply scaled SOI MOSFETs"
-
A. Khakifirooz and D. A. Antoniadis, "Effect of back-gate biasing on the performance and leakage control in deeply scaled SOI MOSFETs," in Proc. IEEE Int. SOI Conf., 2002, pp. 58-59.
-
(2002)
Proc. IEEE Int. SOI Conf.
, pp. 58-59
-
-
Khakifirooz, A.1
Antoniadis, D.A.2
-
17
-
-
0020243830
-
"A precision variable-supply CMOS comparator"
-
SC-17 Dec
-
D. J. Allstot, "A precision variable-supply CMOS comparator," IEEE J. Solid-State Circuits, vol. SC-17, pp. 1080-1087, Dec. 1982.
-
(1982)
IEEE J. Solid-State Circuits
, pp. 1080-1087
-
-
Allstot, D.J.1
-
18
-
-
0037666942
-
"A switched-opamp with fast common-mode feedback"
-
M. Waltari and K. Halonen, "A switched-opamp with fast common-mode feedback," in Proc. ICECS, 1999, pp. 1523-1525.
-
(1999)
Proc. ICECS
, pp. 1523-1525
-
-
Waltari, M.1
Halonen, K.2
-
20
-
-
0030081469
-
"TCAD for analog circuit applications: Virtual devices and instruments"
-
R. W. Dutton, B. Troyanovsky, Z. Yu, E. C. Kan, K. Wang, T. Chen, and T. Amborg, "TCAD for analog circuit applications: virtual devices and instruments," in ISSCC Tech. Dig., 1996, pp. 78-79.
-
(1996)
ISSCC Tech. Dig.
, pp. 78-79
-
-
Dutton, R.W.1
Troyanovsky, B.2
Yu, Z.3
Kan, E.C.4
Wang, K.5
Chen, T.6
Amborg, T.7
-
22
-
-
0026819378
-
"Statistical modeling of device mismatch for analog MOS integrated circuits"
-
Feb
-
C. Michael and M. Ismail, "Statistical modeling of device mismatch for analog MOS integrated circuits," IEEE J. Solid-State Circuits, vol. 27, pp. 154-166, Feb. 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, pp. 154-166
-
-
Michael, C.1
Ismail, M.2
-
23
-
-
84900299278
-
"The influence and modeling of process variation and device mismatch for analog/RF circuit design"
-
Y. Cheng, "The influence and modeling of process variation and device mismatch for analog/RF circuit design," in Proc. IEEE Int. Devices, Circuits and Systems Caracas Conf., 2002, pp. D046-1-D046-8.
-
(2002)
Proc. IEEE Int. Devices, Circuits and Systems Caracas Conf.
-
-
Cheng, Y.1
-
24
-
-
0141940281
-
"A physical compact model of DGMOSFET for mixed-signal circuit applications, part I: Model description"
-
Oct
-
G. Pei, W. Ni, A. V. Kammula, B. A. Minch, and E. C. Kan, "A physical compact model of DGMOSFET for mixed-signal circuit applications, part I: model description," IEEE Trans. Electron Devices, vol. 50, pp. 2135-2143, Oct. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, pp. 2135-2143
-
-
Pei, G.1
Ni, W.2
Kammula, A.V.3
Minch, B.A.4
Kan, E.C.5
-
25
-
-
0004200915
-
-
Englewood Cliffs, NJ: Prentice-Hall
-
B. Razavi, RF Microelectronics. Englewood Cliffs, NJ: Prentice-Hall, 1998.
-
(1998)
RF Microelectronics
-
-
Razavi, B.1
|