The influence and modeling of process variation and device mismatch for analog/rf circuit design

ICCDCS 2002 - 4th IEEE International Caracas Conference on Devices, Circuits and Systems

Volumn , Issue , 2002, Pages

  Cheng, Yuhua ^a  

^a Rockwell Semiconductor Systems   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; MODELS;

ANALOG/RF CIRCUITS; CHANNEL QUANTIZATION; CIRCUIT BEHAVIORS; ELECTRICAL CHARACTERISTIC; INDEPENDENT VARIABLES; NARROW-WIDTH EFFECTS; PROCESS VARIATION; STATISTICAL MODELING;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 84900299278     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCDCS.2002.1004068     Document Type: Conference Paper

References (13)

1. M. Pronath et al., "WiCkeD: analog circuit synthesis incorporating mismatch", Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, pp. 511-514 2000.
2. S. Zanella et al., "Analysis of the impact of intra-die variance on clock skew", 1999 4th International Workshop o Statistical Metrology, pp. 14-17, 1999.
3. M. Pelgrom et al., "Transistor matching in analog CMOS applications", Technical Digest of International Electron Devices Meeting, pp. 915-918, 1998.
4. J. A. Groon et al., "A simple characterization method for MOS transistor mismatching in deep-submicron technology", Proceedings of the 2001 International Conference on Microelectronic Test Structures, pp. 213-218, 2001.
5. T. B. Tarim, et al., "Application of a statistical design methodology to low voltage analog MOS integrated circuits", The 2000 IEEE International Symposium on Circuits and Systems, 2000, Volume 4, pp. 117-120, Geneva, 2000.
6. G. Box, W. G. Hunter, and J. S. Hunter, "Statistics for experiments," John Wiley & Sons, 1978.
7. W. A. Lane, and G. T. Wrixon, " The design of this-thin polysilicon resistors for analog 1C applications," IEEE Trans. On Electron Devices, vol. 36, No. 4, pp. 738-744, 1989.
8. J. B. Shyu, et al., "Random Errors in MOS capacitors," IEEE J. Solid-state Circuits, vol-sc-17, No. 6, pp. 1070-1076, 1982.
9. R. Thewes, et al., "Mismatch of MOSFET small signal parameters under analog operation,"
10. S. Lee et al, "An efficient statistical model using electrical tests for GHz CMOS devices", 5th International Workshop on Statistical Metrology, 2000, pp. 72-75, 2000.
11. Q. Zhang, and J. J. Liou, "SPICE modeling and quick estimation of MOSFET mismatch based on BSIM3 model and parametric tests," IEEE Journal of Solid-State Circuits, Volume: 36 Issue: 10 , pp. 1592-1595, 2000
12. J. Oelun et al., "A physical approach to mismatch modelling and parameter correlations," Proceedings of the 2000 IEEE International Symposium on Circuits and Systems, 2000. Geneva., Volume: 4 , pp. 377-380, 2000.
13. P. G. Drennan and C. C. McAndrew, "A comprehensive MOSFET mismatch model," in Proc. IEEE Int. Electron Device Meeting, 1999, pp. 167-170.