The impact of PMOST bias-temperature degradation on logic circuit reliability performance

Microelectronics Reliability

Volumn 45, Issue 1, 2005, Pages 107-114

  Lee, Yung Huei ^a   Jacobs, Steve ^a   Stadler, Stefan ^a   Mielke, Neal ^a   Nachman, Ramez ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DATA REDUCTION; DEGRADATION; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; MATHEMATICAL MODELS; SIGNAL PROCESSING; TRANSCONDUCTANCE;

BIAS TEMPERATURE; CHANNEL LENGTH; OXIDE STATES; TEMPERATURE DEGRADATION;

LOGIC CIRCUITS;

EID: 10044286895     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2004.05.027     Document Type: Article

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