Effect of trench edge on pMOSFET reliability

Microelectronics Reliability

Volumn 41, Issue 5, 2001, Pages 689-696

  Lee, Yung Huei ^a   Linton, Tom ^a   Wu, Ken ^a   Mielke, Neal ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER CONCENTRATION; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DEGRADATION; HOT CARRIERS;

PROXIMITY EFFECTS; SHALLOW TRENCH ISOLATION (STI);

MOSFET DEVICES;

EID: 0035340240     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(01)00002-6     Document Type: Article

References (18)

1. Hot-carrier induced punchthrough (HEIP) effect in submicrometer pMOSFETs
2. Simulation of CMOS circuit degradation due to hot-carrier effects
3. Enhanced hot-carrier induced degradation in shallow trench isolated narrow channel pMOSFET's
4. Channel width dependence of hot-carrier induced degradation in shallow trench isolated pMOSFETs
5. New hot-carrier degradation mode and lifetime prediction method in quarter-micrometer pMOSFET
6. A new mode of hot carrier degradation in 0.18 μm CMOS technologies
7. Hot-carrier reliability characteristics of narrow-width MOSFETs
8. NBTI - Channel hot carrier effects in pMOSFETs in advanced CMOS technologies
9. + polysilicon gate pMOSFETs induced by bias temperature (BT) instability
10. Three hot-carrier degradation mechanisms in deep-submicron pMOSFET's
11. Hot-carrier damage in AC-stressed deep submicrometer CMOS technologies
12. Channel length and width dependence of hot-carrier hardness in Fluorinated MOSFET's
13. Simulation of p- and n-MOSFET hot-carrier degradation in CMOS circuits
14. Accelerated stress testing
15. Role of hydrogen anneal in thin gate oxide for multi-metal - Layer CMOS process
16. A shallow trench isolation using LOCOS edge for preventing corner effects for 0.25/0.18 μm CMOS technologies and beyond