Design of a Fault Tolerant Solid State Mass Memory

IEEE Transactions on Reliability

Volumn 52, Issue 4, 2003, Pages 476-491

  Cardarilli, Gian Carlo ^a   Leandri, Alessandro ^a   Marinucci, Panfilo ^b   Ottavi, Marco ^a   Pontarelli, Salvatore ^a   Re, Marco ^a   Salsano, Adelio ^a  

^a UNIVERSITY OF ROME TOR VERGATA   (Italy)

^b Consorzio Ulisse ^*  (Italy)

Author keywords

Codes; Memory architecture; Redundancy; Seit checking; Solid state mass memory; SSMM

Indexed keywords

MEMORY ARCHITECTURE; SELF CHECKING; SOLID STATE MASS MEMORY (SSMM); SWITCHING MATRIX;

BANDWIDTH; COMPUTER SIMULATION; CONTROL EQUIPMENT; DYNAMIC RANDOM ACCESS STORAGE; ERROR DETECTION; MICROCONTROLLERS; SOLID STATE DEVICES; SPACE APPLICATIONS; SYSTEMS ANALYSIS;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 0742324992     PISSN: 00189529     EISSN: None     Source Type: Journal    
DOI: 10.1109/TR.2003.821938     Document Type: Article

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