New techniques for accelerating fault injection in VHDL descriptions

Proceedings - 6th IEEE International On-Line Testing Workshop

Volumn , Issue , 2000, Pages 61-66

  Parrotta, B ^a   Rebaudengo, M ^a   Reorda, M S ^a   Violante, M ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION LANGUAGES; SOFTWARE TESTING;

COMMON FEATURES; CPU TIME; DYNAMIC METHOD; FAULT INJECTION; TOP DOWN DESIGN; TYPICAL FAULTS; VHDL DESCRIPTION; VHDL SIMULATION;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 0002475610     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2000.856613     Document Type: Conference Paper

References (13)

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