A Fault-tolerant 176 Gbit Solid State Mass Memory Architecture

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn Part F5373300, Issue , 2000, Pages 173-180

  Cardarilli, G C ^a   Marinucci, P ^a,b   Ottavi, M ^a,b   Salsano, A ^a  

^a UNIVERSITY OF ROME TOR VERGATA   (Italy)

^b Consortium ULISSE ^*

Author keywords

[No Author keywords available]

Indexed keywords

ERROR CORRECTION; FAULT TOLERANCE; RADIATION HARDENING; SPACE APPLICATIONS; FAULT TOLERANT COMPUTER SYSTEMS; HIERARCHICAL SYSTEMS; SOLID STATE DEVICES;

ERROR CORRECTION CODES; FAULT-TOLERANT; FINE GRANULARITY; HARD FAILURES; HIERARCHICAL STRUCTURES; MAIN PARAMETERS; MEMORY RELIABILITY; PERFORMANCE INDICES; SOFT ERROR; SOLID STATE MASS MEMORY;

MEMORY ARCHITECTURE; COMPUTER ARCHITECTURE;

ERROR CORRECTION CODES (ECC); SOLID STATE MASS MEMORY (SSMM);

EID: 0034509287     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2000.887155     Document Type: Conference Paper

References (5)

1. G.C. Cardarilli, P. Marinucci, A. Salsano, "Fault-tolerant Solid State Mass Memory for Satellite Applications", IEEE Instrumentation and Measurement Conference, St. Paul, Minnesota, USA, May 18-21, 1998TC'98.
2. G.C. Cardarilli, P. Marinucci, S. Bertazzoni, M. Salmeri, A. Salsano, "Design of Fault-tolerant Solid State Mass Memory", DFT'99, Albuquerque, NM, October 1999.
3. G.C. Cardarilli, P. Marinucci, A. Salsano, "Development of an Evaluation Model for the Design of Fault-tolerant Solid State Mass Memory", accepted for the presentation to ISCAS 2000, Geneva, Switzerland.
4. M.P. Kluth, F. Simon, J.Y. Le Gall, E. Muller, "Design of a fault tolerant 100 Gbits solid-state mass memory for satellites", VLSI Test Symposium, 1996., Proceedings of 14th, 1996.
5. Fichna, T.; Gartner, M.; Gliem, F.; Rombeck, F. "Fault-tolerance of spaceborne semiconductor mass memories", Fault-Tolerant Computing, 1998. Digest of Papers. Twenty-Eighth Annual International Symposium on, 1998.