Parallel signature analysis design with bounds on aliasing

IEEE Transactions on Computers

Volumn 46, Issue 4, 1997, Pages 425-438

  Saxena, Nirmal R ^a,b   McCluskey, Edward J ^a,c  

^a IEEE

^b HEWLETT PACKARD ENTERPRISE   (United States)

^c Stanford University   (United States)

Author keywords

Aliasing probability bounds; Linear feedback shift registers; Multiple input signature registers (MISR); Parallel signature designs; Random testing; Signature analysis

Indexed keywords

LOGIC CIRCUITS; LOGIC DESIGN; POLYNOMIALS; PROBABILITY; SHIFT REGISTERS; VLSI CIRCUITS;

ALIASING PROBABILITY BOUNDS; MULTIPLE INPUT SIGNATURE REGISTERS (MISR); SIGNATURE ANALYSIS;

MICROPROCESSOR CHIPS;

EID: 0031121686     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.588057     Document Type: Article

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